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Order Number: XPC750EC/D Rev 2, 09/2001
Semiconductor Products Sector
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Advance Information
XPC750P RISC Microprocessor Hardware Specifications
This document describes pertinent physical characteristics of the XPC750P, a process-remapped version of the MPC750. This part has been previously described jointly with the MPC750 in the MPC750 RISC Microprocessor Hardware Specifications (MPC750EC/D Rev 1); however, it is now being described separately because the MPC750 is available over much wider operating conditions (including extended temperature conditions). The XPC750P described herein will only be available at the restricted operating conditions described in Table 3. This document describes the XPC750P; however, unless otherwise noted, all information here applies also to the XPC740P. The XPC750P and XPC740P are implementations of the PowerPCTM family of reduced instruction set computing (RISC) microprocessors. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor User's Manual. The MPC750 family has been implemented in several semiconductor fabrication processes. Different processes require different supply voltages and may have other electrical differences. The implementations are, in general, functionally equivalent but may represent different revisions of the design with regard to errata. A companion document, called a Part Number Specification, is created to describe errata or specification variances that are unique to a particular revision. Part Number Specifications, if applicable, are available at the same website, http://www.mot.com/PowerPC, where this document is found.
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2001. All rights reserved.
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
As a designator to distinguish between MPC750 implementations in various processes, a suffix is added to the MPC750 part number as shown in Table 1.
Table 1. MPC750 Microprocessors from Motorola
Part Number MPC750A, MPC740A XPC750P, XPC740P Process 0.29 m CMOS, 5LM 0.19 m CMOS, 5LM Core Voltage 2.6 V 1.9 V I/O Voltage 3.3 V 3.3 V 5-Volt Tolerant No No
This document will describe only the XPC750P implementation with its unique supply voltages, package (decoupling capacitors are added on the package), and unique AC timing specifications. Major subsections of this document which are identical to the MPC750 Hardware Specification are not repeated here to reduce confusion. Please refer to the MPC750 document for those unchanged subsections. This document contains the following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.4.1, "DC Electrical Characteristics" Section 1.4.2, "AC Electrical Characteristics" Section 1.4.2.1, "Clock AC Specifications" Section 1.4.2.2, "60x Bus Input AC Specifications" Section 1.4.2.3, "60x Bus Output AC Specifications" Section 1.4.2.4, "L2 Clock AC Specifications" Section 1.4.2.5, "L2 Bus Input AC Specifications" Section 1.4.2.6, "L2 Bus Output AC Specifications" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Document Revision History" To locate any published errata or updates for this document, refer to the website at http://www.mot.com/PowerPC/.
3 3 3 4 4 7 8 9 11 12 15 16 17 17 17 20 22
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
1.1 Overview
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.2 Features
This section is unchanged from the MPC750 Hardware Specification except as relates to supply voltage; refer to that document for feature information and to this document for applicable supply voltage.
1.3 General Parameters
The following list provides a summary of the general parameters of the XPC750P: Technology Die size Transistor count Logic design Packages 0.18 m CMOS, five-layer metal 7.56 mm x 8.79 mm (67 mm2) 6.35 million Fully-static XPC740P: Surface mount 255 ceramic ball grid array (CBGA) without L2 interface XPC750P: Surface mount 360 ceramic ball grid array (CBGA) with L2 interface Core power supply: I/O power supply 1.9V 100 mV @300 and 333MHz 2.05V 50mV @366 and 400MHz 3.3V 5% V dc
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
1.4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the XPC750P.
1.4.1 DC Electrical Characteristics
The tables in this section describe the XPC750P DC electrical characteristics. Table 2 provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage Input voltage Storage temperature range Notes: 1. Functional and tested operating conditions are given in Figure 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd/L2OVdd by more than 0.3V at any time including during power-on reset. 3. Caution: OVdd/L2OVdd must not exceed Vdd/AVdd by more than 2.0V at any time including during power-on reset. 4. Caution: Vdd/AVdd/L2AVdd must not exceed OVdd/L2OVdd by more than 0.4V at any time including during power-on reset. 5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 1. Symbol Vdd AVdd L2AVdd OVdd L2OVdd Vin Tstg XPC750P Value -0.3 to 2.5 -0.3 to 2.5 -0.3 to 2.5 -0.3 to 3.6 -0.3 to 3.6 -0.3 to 3.6 -55 to 150 Unit V V V V V V C Notes 4 4 4 3,5 3,5 2
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 1 shows the permitted undershoot and overshoot voltage on the XPC750P.
4V (L2)OVdd + 5% (L2)OVdd
VIH
VIL Gnd Gnd - .3V Gnd - 1.0V Not to exceed 10% of tSYSCLK
Figure 1. Overshoot/Undershoot Voltage
Table 3 provides the recommended operating conditions for the XPC750P.
Table 3. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage Input voltage Die-junction temperature Symbol Vdd AVdd L2AVdd OVdd L2OVdd Vin Tj 300, 333MHz 1.9 100mv 1.9 100mv 1.9 100mv 3.3 165mv 3.3 165mv GND to OVdd 0 to 105 366MHz 2.05 50mv 2.05 50mv 2.05 50mv 3.3 165mv 3.3 165mv GND to OVdd 0 to 105 400MHz 2.05 50mv 2.05 50mv 2.05 50mv 3.3 165mv 3.3 165mv GND to OVdd 0 to 65 Unit V V V V V V C
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 4 provides the package thermal characteristics for the XPC750P.
Table 4. Package Thermal Characteristics
Characteristic CBGA package thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) Symbol JC JB Value 0.03 3.8 Rating C/W C/W
Note: Refer to Section 1.8, "System Design Information," for more details about thermal management.
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
The XPC750P incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digitalto-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See the MPC750 RISC Microprocessor User's Manual for more information on the use of this feature. Specifications for the thermal sensor portion of the TAU are found in Table 5.
Table 5. Thermal Sensor Specifications
At recommended operating conditions (See Table 3.)
Characteristic Temperature range Comparator settling time Resolution
Min 0 20 4
Max 127 -- --
Unit C s C
Notes 1 2 3
Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit's raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see Motorola Application Note AN1800/D, "Programming the Thermal Assist Unit in the MPC750 Microprocessor". 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. Guaranteed by design and characterization.
Table 6 provides the DC electrical characteristics for the XPC750P.
Table 6. DC Electrical Specifications
At recommended operating conditions (See Table 3.)
Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = OVdd Hi-Z (off-state) leakage current, Vin = OVdd Output high voltage, IOH = -6 mA Output low voltage, IOL = 6 mA Capacitance, Vin = 0 V, f = 1 MHz
Symbol VIH VIL CVIH CVIL Iin ITSI VOH VOL Cin
Min 2 -0.3 2.4 -0.3 -- -- 2.4 -- --
Max OVdd + 0.3 0.8 OVdd + 0.3 0.4 30 30 -- 0.4 5.0
Unit V V V V A A V V pF
Notes 2,3
2
2,3 2,3,5
3,4
Notes: 1. Nominal voltages; See Figure 3 for recommended operating conditions. 2. For 60x bus signals, the reference is OVdd while L2OVdd is the reference for the L2 bus signals. 3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both OVdd and Vdd vary by either +5% or -5%).
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 7 provides the power consumption for the XPC750P.
Table 7. Power Consumption for XPC750P
Processor (CPU) Frequency Unit 300 MHz 333 MHz 366MHz 400 MHz Notes
Full-On Mode Typical Maximum 3.4 5.5 4.2 6.0 Doze Mode Maximum 2.5 2.65 Nap Mode Maximum 700 4733 766 800 mW 1, 2 2.85 3.0 W 1, 2 4.6 6.6 5.0 7.2 W W 1, 3, 4 1, 2, 4
Sleep Mode Maximum 650 665 685 700 mW 1, 2
Sleep Mode--PLL and DLL Disabled Typical Maximum 450 600 450 600 450 600 450 600 mW mW 1, 3 1, 2
Notes: 1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mW and L2AVdd = 15 mW. 2. Maximum power is measured at Vdd = 2.0V. 3. Typical power is an average value measured at Vdd = AVdd = L2AVdd = 1.9V, OVdd = L2OVdd = 3.3V in a system executing typical applications and benchmark sequences. 4. Full-On mode is measured using worst-case instruction sequence.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the XPC750P. After fabrication, parts are sorted by maximum processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency. See Section 1.10, "Ordering Information."
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
1.4.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 2.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3.)
300 MHz Num Characteristic Min Processor frequency VCO frequency SYSCLK frequency 1 2, 3 4 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at 1.4V SYSCLK jitter Internal PLL relock time 250 500 33 10 -- 40 -- -- Max 300 600 100 30 2 60 150 100
333 MHz Min 250 500 33 10 -- 40 -- -- Max 333 666 100 30 2 60 150 100
366 MHz Min 250 500 33 10 -- 40 -- -- Max 366 733 100 30 2 60 150 100
400 MHz Unit Min 250 500 33 10 -- 40 -- -- Max 400 800 100 30 2 60 150 100 MHz MHz MHz ns ns % ps s 2 3 4 5 1 Notes
Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8.1, "PLL Configuration," for valid PLL_CFG[0-3] settings 2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V. 3. Timing is guaranteed by design and characterization. 4. The total input jitter (short term and long term combined) must be under 150 ps. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 2 provides the SYSCLK input timing diagram.
1 4 4 CVIH 2 3
SYSCLK
VM
VM
VM CVIL
VM = Midpoint Voltage (1.4V)
Figure 2. SYSCLK Input Timing Diagram
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.2 60x Bus Input AC Specifications
Table 9 provides the 60x bus input AC timing specifications for the XPC750P as defined in Figure 3 and Figure 4. Input timing specifications for the L2 bus are provided in Section 1.4.2.5, "L2 Bus Input AC Specifications.
Table 9. 60x Bus Input AC Timing Specifications1
At recommended operating conditions (See Table 3.)
300,333,366,400 MHz Num Characteristic Min 10a 10b 10c 11a 11b 11c Address/Data/Transfer Attribute Inputs Valid to SYSCLK (Input Setup) All Other Inputs Valid to SYSCLK (Input Setup) Mode select input setup to HRESET (DRTRY, TLBISYNC) SYSCLK to Address/Data/Transfer Attribute Inputs Invalid (Input Hold) SYSCLK to All Other Inputs Invalid (Input Hold) HRESET to mode select input hold (DRTRY, TLBISYNC) 2.5 2.5 8 0 0 0 Max -- -- -- -- -- -- ns ns tsysclk ns ns ns 2 3 4,5,6,7 2 3 4,6,7 Unit Notes
Notes: 1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/Data/Transfer Attribute inputs are composed of the following--A[0-31], AP[0-3], TT[0-4], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other signal inputs are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4.). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Guaranteed by design and characterization. 7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
Figure 3 provides the input timing diagram for the XPC750P.
SYSCLK
10a 10b 11a 11b VM
ALL INPUTS
VM = Midpoint Voltage (1.4V)
Figure 3. Input Timing Diagram
Figure 4 provides the mode select input timing diagram for the XPC750P.
HRESET
10c VIH
11c
MODE PINS VIH = 2.0V
Figure 4. Mode Select Input Timing Diagram
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.3 60x Bus Output AC Specifications
Table 10 provides the 60x bus output AC timing specifications for the XPC750P as defined in Figure 5. Output timing specifications for the L2 bus are provided in Section 1.4.2.6, "L2 Bus Output AC Specifications."
Table 10. 60x Bus Output AC Timing Specifications1
At recommended operating conditions (See Table 3.), CL = 50 pF2
300,333,366,400 MHz Num Characteristic Min 12 13 14 15 16 17 18 19 20 21 SYSCLK to Output Driven (Output Enable Time) SYSCLK to Output Valid (TS, ABB, ARTRY, DBB) SYSCLK to all other Outputs Valid (all except TS, ABB, ARTRY, DBB) SYSCLK to Output Invalid (Output Hold) SYSCLK to Output High Impedance (all except ABB, ARTRY, DBB) SYSCLK to ABB, DBB High Impedance after precharge SYSCLK to ARTRY High Impedance before precharge SYSCLK to ARTRY Precharge Enable Maximum Delay to ARTRY Precharge SYSCLK to ARTRY High Impedance After Precharge 0.5 -- -- 1.0 -- -- -- 0.2*tsysclk +1.0 -- -- Max -- 5.0 5.0 -- 6.0 1.0 5.5 -- 1 2 ns ns ns ns ns tsysclk ns ns tsysclk tsysclk 5 5 3 8 4,6,8 8 3,4,7 4,7 4,7,8 Unit Notes
Notes: 1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timing are measured at the pin. 2. All maximum timing specifications assume CL = 50 pF. 3. This minimum parameter assumes CL = 0 pF. 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question. 5. Output signal transitions from GND to 2.0V or OVdd to 0.8V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk. 8. Guaranteed by design and characterization.
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
Figure 5 provides the output timing diagram for the XPC750P.
SYSCLK
VM VM VM
14 12
15 16
ALL OUTPUTS (Except TS, ABB, ARTRY, DBB)
13 13 15 16
TS
17
ABB, DBB
21 20 19 18
ARTRY
VM = Midpoint Voltage (1.4V)
Figure 5. Output Timing Diagram
1.4.2.4 L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2 divisor ratio. See Table 15 for example core and L2 frequencies at various divisors. Table 11 provides the potential range of L2CLK output AC timing specifications as defined in Figure 6. The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the XPC750P core clock at the SRAMs. The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of the XPC750P will be a function of the AC timings of the XPC750P, the AC timings for the SRAM, bus loading, and printed circuit board trace length. Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 11. Therefore functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater. L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
timings of Table 12 and Table 13 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Figure 12 and Table 13 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK.
Table 11. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3.)
300 MHz Num Characteristic Min L2CLK frequency 22 23 L2CLK cycle time L2CLK duty cycle Internal DLL-relock time DLL capture window L2CLKOUT output-tooutput skew L2CLKOUT output jitter 640 80 3.3 50 -- Max 300 12.5
333 MHz Min 80 3 50 640 -- Max 333 12.5
366 MHz Min 80 2.7 50 640 -- Max 366 12.5
400 MHz Unit Min 80 2.5 50 640 -- Max 400 12.5 MHz ns % L2CLK 2 3 1,4 Notes
0.5
12.5 50
0.5
12.5 50
0.5
12.5 50
0.5
12.5 50
ns ps
5 6
150
150
150
150
ps
6
Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUTC, L2CLK_OUTD, and L2SYNC_OUT pins. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. The minimum skew value allows several taps of negative adjustment without rolling over to the maximum tap. Exceptionally short paths from L2SYNC_OUT to L2SYNC_IN on the XPC750P has been observed to result in missing L2CLKOUT pulses or L2CLKOUT pulses of incorrect duty cycle. 6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis.
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
The L2CLK_OUT timing diagram is shown in Figure 6.
L2 Single-Ended Clock Mode
22
23
VM
VM
VM
L2CLK_OUTA
VM
VM
VM
L2CLK_OUTB
VM
VM
VM
L2SYNC_OUT
VM = Midpoint Voltage (L2OVdd/2)
L2 Differential Clock Mode
22
L2OVdd L2CLK_OUTB
VM
23
VM
VM
L2CLK_OUTA GND
VM VM VM
L2SYNC_OUT
VM = Midpoint Voltage (L2OVdd/2)
Figure 6. L2CLK_OUT Output Timing Diagram
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.5 L2 Bus Input AC Specifications
The L2 bus input interface AC timing specifications are found in Table 12.
Table 12. L2 Bus Input Interface AC Timing Specifications1
At recommended operating conditions (See Table 3.)
Num
Characteristic
Processor Frequency 300-400 MHz Min Max 1.0 -- --
Unit
Notes
29,30 24 25
L2SYNC_IN rise and fall time Data and parity input setup to L2SYNC_IN L2SYNC_IN to data and parity input hold
-- 1.5 0
ns ns ns
2
Notes: 1. All input specifications are measured from the TTL level (0.8V or 2.0V) of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN. Input timings are measured at the pins (See Figure 7). 2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.
Figure 7 shows the L2 bus input timing diagrams for the XPC750P.
29 30
L2SYNC_IN
VM
24
25
ALL INPUTS
VM = Midpoint Voltage (1.4V)
Figure 7. L2 Bus Input Timing Diagrams
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Electrical and Thermal Characteristics
1.4.2.6 L2 Bus Output AC Specifications
Table 13 provides the L2 bus output interface AC timing specifications for the XPC750P as defined in Figure 8.
Table 13. L2 Bus Output Interface AC Timing Specifications1
At recommended operating conditions (See Table 3.), CL = 20 pF3
Num
Characteristic
L2CR[14-15]
Core Frequency 300-400MHz Min Max 4.2 4.7 4.9 5.2 -- -- -- -- 3.5 4.0 4.2 4.5
Notes
26
L2SYNC_IN to output valid
002 01 10 11
-- -- -- -- 0.75 1.25 1.45 1.75 -- -- -- --
27
L2SYNC_IN to output hold
002 01 10 11
4 4 4 4
28
L2SYNC_IN to high impedance
002 01 10 11
Notes: 1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the TTL level (0.8V or 2.0V) of the signal in question. The output timings are measured at the pins. 2.The outputs are valid for both single-ended and differential L2CLK modes. For flow-thru and pipelined reg-reg synchronous burst RAMs, L2CR[14-15] = 00 is recommended. For pipelined delay-write synchronous burst SRAMs, L2CR[14- 15] = 01 is recommended. 3. All maximum timing specifications assume CL =20 pF. 4. This measurement assumes CL = 5 pF.
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XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Figure 8 shows the L2 bus output timing diagrams for the XPC750P.
VM
VM
L2SYNC_IN
26 27
ALL OUTPUTS
28
L2DATA BUS
VM = Midpoint Voltage (1.4V)
Figure 8. L2 Bus Output Timing Diagrams
1.4.3 IEEE 1149.1 AC Timing Specifications
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.5 Pin Assignments
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.6 Pinout Listings
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.7 Package Description
The following sections provide the package parameters and mechanical dimensions for the XPC740P, 255 CBGA packages.
1.7.1 Parameters for the XPC740P
The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height 21 x 21 mm 255 (16 x 16 ball array - 1) 1.27 mm (50 mil) 2.45 mm
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Package Description
Maximum module height Ball diameter
3.00 mm 0.89 mm (35 mil)
1.7.2 Mechanical Dimensions of the XPC740P
Figure 9 provides the mechanical dimensions and bottom surface nomenclature of the XPC740P, 255 CBGA package.
2X
0.2
A1 CORNER
D
A
C 0.15 C E E1
2X
0.2 B D1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY.
M
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A
Millimeters DIM A A1 A2 b D D1 e E E1 M Min Max 2.45 3.00 0.79 0.99 0.9 1.10 0.82 0.93 21.00 BSC 8.3 8.5 1.27 BSC 21.00 BSC 9.0 9.2 2.00
e/2
A2 A1 A
e
255X
e/2 b 0.3 C A B 0.15 C
Figure 9. Mechanical Dimensions and Bottom Surface Nomenclature of the XPC740P
1.7.3 Parameters for the XPC750P
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA).
18
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Package Description
Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter
25 x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.65 mm 3.20 mm 0.89 mm (35 mil)
1.7.4 Mechanical Dimensions of the XPC750P
Figure 10 provides the mechanical dimensions and bottom surface nomenclature of the XPC750P, 360 CBGA package.
PIN A1 INDEX 2X
0.2 B A
360X
D
1
0.15 A 0.25 A
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE AND UNDERFILL. ACTUAL SIZE OF THIS AREA MAY BE SMALLER THAN SHOWN. D3 AND E3 ARE THE MINIMUM CLEARANCE FROM THE PACKAGE EDGE TO THE CHIP CAPACITORS. 5. CAPACITORS MAY NOT BE PRESENT ON ALL DEVICES. 6. CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON PACKAGE TOP. 7. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
MILLIMETERS MIN MAX 2.72 3.20 0.80 1.00 1.10 1.30 --0.60 0.82 0.90 0.82 0.93 25.00 BSC 22.86 BSC --- 12.50 2.75 --6.00 9.00 1.27 BSC 25.00 BSC 22.86 BSC --- 14.30 3.00 --8.00 11.00
E2 E4 E
0.35 A
2X
0.2
2X
D3
D4 D2 TOP VIEW D1
18X
2X
E3
C
e
18X
C L
W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10111213141516171819
e
A3 A4 C L E1 A SIDE VIEW A2 A1
DIM A A1 A2 A3 A4 b D D1 D2 D3 D4 e E E1 E2 E3 E4
360X
b 0.3 A B C 0.15 A
BOTTOM VIEW
Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the XPC750P
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
19
System Design Information
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the XPC750P.
1.8.1 PLL Configuration
The XPC750P's PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the XPC750P is shown in Table 14 for nominal frequencies.
Table 14. XPC750P Microprocessor PLL Configuration
Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0-3] Bus-toCore Multiplier 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x Core-to VCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 260 (520) 280 (560) 250 (500) 275 (550) 300 (600) 325 (650) 350 (700) 266 (533) 300 (600) 333 (666) 366 (733) 400 (800) 262 (525) 300 (600) 330 (660) 375 (750) Bus 33.3 MHz Bus 40 MHz Bus 50 MHz Bus 66.6 MHz Bus 75 MHz Bus 83.3 MHz 250 (500) 292 (594) 333 (666) 375 (750) Bus 100 MHz 300 (600) 350 (700) 400 (800)
1000 1110 1010 0111 1011 1001 1101 0101 0010
20
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information Table 14. XPC750P Microprocessor PLL Configuration (Continued)
Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0-3] Bus-toCore Multiplier 7.5x 8x Core-to VCO Multiplier 2x 2x Bus 33.3 MHz 250 (500) 1100 0011 1111 266 (533) PLL off/bypass PLL off Bus 40 MHz 300 (600) 320 (640) Bus 50 MHz 375 (750) 400 (800) Bus 66.6 MHz Bus 75 MHz Bus 83.3 MHz Bus 100 MHz
0001
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs
Notes: 1. PLL_CFG[0-3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the XPC750P; see Section 1.4.2.1, "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the XPC750P regardless of the SYSCLK input.
The XPC750P generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the XPC750P. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the XPC750P to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface. The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the XPC750P core, and the phase adjustment range that the L2 DLL supports. Table 15 shows various example L2 clock frequencies that can be obtained for a given set of core frequencies.
Table 15. Sample Core-to-L2 Frequencies
Core Frequency in MHz 300 333 366 400 /1 300 333 366 400 /1.5 200 222 244 266 /2 150 167 183 200 /2.5 120 133 146 150 /3 100 111 122 133
Note: The core and L2 frequencies are for reference only. Some configurations may select core or L2 frequencies which are not useful, not supported, or not tested for by the XPC750P; see Section 1.4.2.4, "L2 Clock AC Specifications," for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz.
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
21
Document Revision History
1.8.2 PLL Power Supply Filtering
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.8.3 Decoupling Recommendations
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.8.4 Connection Recommendations
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.8.5 Output Buffer DC Impedance
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.8.6 Pull-up Resistor Requirements
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.8.7 Thermal Management Information
This section is unchanged from the MPC750 Hardware Specification; refer to that document for this information.
1.9 Document Revision History
Table 16. Document Revision History
Document Revision Rev 0 Substantive Changes Separated XPC750P information from MPC750 Hardware Specification because of increasing diversity in operating conditions, particularly core voltage and operating temperature. Also, expanded discussion of L2CLK AC specifications to clarify and change maximum frequency of L2 operation; limited L2OVdd to 3.3V 5% only.; added minimum DLL skew specification; updated L2 AC timings in Table 13. Rev 1 Rev 2 Changed maximum voltage for Vdd, AVdd, and L2AVdd in Table 2 to 2.5 volts. Revised Figure 10.
22
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Ordering Information
1.10 Ordering Information
This section provides the part numbering nomenclature for the XPC750P. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. Figure 11 provides the Motorola part numbering nomenclature for the XPC750P. In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original production design. The bus divider may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only.
.
XPC 750 P RX XXX X E
Product Code Part Identifier (740 or 750) Part Modifier Revision Level (Contact Local Motorola Sales Office) Application Modifier (L =1.9V core, 0o to105o Tj ) (R = 2.05Vcore, 0o to 65o Tj ) Processor Frequency Package (RX = BGA)
Figure 11. Motorola Part Number Key
XPC750P RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
23
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Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or 1-303-675-2140; World Wide Web Address: http://ldc.nmd.com/ JAPAN: Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd Silicon Harbour Centre 2, Dai King Street Tai Po Industrial Estate Tai Po, New Territories, Hong Kong TOUCHTONE 1-602-244-6609; US & Canada ONLY (800) 774-1848; World Wide Web Address: http://sps.motorola.com/mfax INTERNET: http://motorola.com/sps Technical Information: Motorola Inc. SPS Customer Support Center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com Document Comments: FAX (512) 933-2625, Attn: RISC Applications Engineering World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/netcomm http://www.motorola.com/Coldfire
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